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jsspace 发表于 2016-10-11 11:34  ! G, ?" a3 n- ]% s: d) v
漏液不可以接受，不管是否灌胶。
4 }* b3 _, i' ?' d" [8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to, N/ \% l+ K" ?$ Q7 I G e' r
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.$ R2 W J0 j. B. [4 j$ C7 J
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:
2 c5 N5 ^5 M- J+ Xa) Opening of the ground fuse,
q% g5 e4 X8 h7 n- C* B9 P- [1 Cb) Charring of the cheesecloth or tissue paper,! g7 V7 |% b" ^0 J! \0 g
c) Emission of flame or molten material from the unit,
5 v$ I, S/ v& j6 [# z! V+ v' K% w- hd) Ignition or dripping of a compound from the unit,. B$ l! [& [; I, P; X" `/ w
e) Exposure of live parts that pose a risk of electric shock under the requirements for9 o* M2 o0 P' G6 }$ m7 F
accessibility of 7.2, or
* P" b( ?5 b$ P& d. vf) Breakdown during the subsequent dielectric voltage withstand test.' _4 F; f! K8 t: } i
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)
; b4 E R' @; Y2 rthrough (f) occurs.
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8.7.2 Component failure test: T( L' A- _2 }+ X y4 J Z
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall" u" }5 H* }- V! \
not exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In/ q0 M* D% Z! T2 u* }. u8 S
preparation for component failure tests, the equipment, circuit diagrams, and component specifications* R9 g; \ x! k# s, O
are examined to determine those fault conditions that might reasonably be expected to occur. Examples/ l! R% B5 V! e' P t: P1 K
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open8 _: F* U% a! k' |1 c
circuits of resistors and internal faults in integrated circuits.1 B. m4 N4 R/ [6 b9 V$ q
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need1 j4 t( z2 \( L( i1 j, L6 a: G% W/ O
not be evaluated for component failure.+ V# @) K4 d1 t8 A' z
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock
2 K! d5 Y: T0 I5 y3 t6 N# mneed not be subject to this test.
/ d$ t- J6 O/ U& j) o8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each7 u& ]0 ?9 k4 O* `* j, p
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as5 P2 D6 p4 D) I1 l9 c Z% n% m8 s
determined by no visual.1 P; a+ d1 ]# V+ B9 `# c
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再核对一下标准看有没有答案？
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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