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jsspace 发表于 2016-10-11 11:34  1 ^$ Q. }: Q5 a
漏液不可以接受，不管是否灌胶。
6 d# \$ k" l) @! `8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to# @( k4 {1 E5 w' A
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.& O/ [9 J/ e7 r! n' X* g5 \
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:4 P9 B$ E) ]7 p% V8 Y
a) Opening of the ground fuse,/ Z* d/ l3 q6 [
b) Charring of the cheesecloth or tissue paper,+ m i) ~3 H5 M
c) Emission of flame or molten material from the unit,8 b' M2 e0 A0 W8 @2 Y
d) Ignition or dripping of a compound from the unit,
. g( g* G9 b( Z; u* M% ?3 e- Y" |7 q( Ae) Exposure of live parts that pose a risk of electric shock under the requirements for( I O/ P3 m/ \; A# {9 j" y$ a
accessibility of 7.2, or
. x% c) K& {4 M" c% e- ef) Breakdown during the subsequent dielectric voltage withstand test.- q; }5 E0 F( A
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)$ |" n3 Q: M3 P) D& R; q* ^
through (f) occurs.
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4 H, \: {7 A- }8.7.2 Component failure test1 K' J0 S8 h. H+ s2 `
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall) m" N$ R& C/ f
not exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In- J9 s1 s% p9 _/ }
preparation for component failure tests, the equipment, circuit diagrams, and component specifications9 a6 B7 A0 h' _7 S' ~: ?
are examined to determine those fault conditions that might reasonably be expected to occur. Examples
2 X. B0 q# i. [+ w9 ~, zinclude: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open1 t4 @6 T) F8 G
circuits of resistors and internal faults in integrated circuits.) k8 i4 }( i8 z9 `
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
/ Q/ Y4 Z _8 Q4 gnot be evaluated for component failure.9 u( M% f* M8 @5 q8 [+ c6 ~/ p
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock
' n; t z0 I) ]$ w0 aneed not be subject to this test.
' F" j, h0 a# S3 l3 [8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each
' k1 [) V! U5 B& itest shall continue until either the unit is no longer operable, or until conditions are obviously stable (as
$ T" _/ Q* O2 |$ F4 l. e6 udetermined by no visual.
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5 \- h2 H) k! n# X3 p8 ~. `) D+ ]) M6 n* d6 ]; h4 R% a) I
再核对一下标准看有没有答案？
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39