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jsspace 发表于 2016-10-11 11:34 
* ^( V( L& Y* R+ r) v1 P/ o' e4 V漏液不可以接受，不管是否灌胶。
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8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to/ `7 z5 S" T% }4 D& Z7 t
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.6 |5 G0 e8 A! J5 c
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:
7 C P! |! C4 ba) Opening of the ground fuse,
3 ~% |. ~1 V. U3 G9 z" R3 mb) Charring of the cheesecloth or tissue paper,
: d/ h* R& g/ d1 v( t3 n+ L0 I# pc) Emission of flame or molten material from the unit,
0 ]- S! f4 O$ R0 f' l8 S$ ]4 f, _d) Ignition or dripping of a compound from the unit,
( V5 n0 P, P0 d! _6 }& {e) Exposure of live parts that pose a risk of electric shock under the requirements for6 L% W, Q7 L& g1 s; a9 ~ Y D2 I
accessibility of 7.2, or
; P0 c- Z+ m. |* f% u; a: {f) Breakdown during the subsequent dielectric voltage withstand test.
6 h' `: r. O4 g% x: JOpening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)
4 b* U; G9 h9 T! ]: Athrough (f) occurs.
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% m- B2 B i9 w4 @# Y. V* Y3 g) w: ?& Q8.7.2 Component failure test- @0 y, t2 j& O" ?" v% S
8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall
/ }! t8 u/ g, f- I% q4 P3 V" Qnot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In' {" L+ p/ n# u5 Y6 O4 }7 p7 ?( A
preparation for component failure tests, the equipment, circuit diagrams, and component specifications
& V2 y# N1 |" U% k+ D6 @are examined to determine those fault conditions that might reasonably be expected to occur. Examples
: X- G- V- ^3 @6 _0 u1 ~% [include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open+ O0 n* v9 o# N0 f; g
circuits of resistors and internal faults in integrated circuits.
) a% z2 _: c9 G5 r. c6 TException No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need
) K$ s* _* ~* g2 u: d- l# ?not be evaluated for component failure.+ u U6 s {- I3 l
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock
; D: N+ n& Q* {4 U2 i9 y1 Q/ C7 uneed not be subject to this test.7 _" P+ T: M5 k0 I$ }
8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each
+ A5 S1 H/ m7 o7 k' Xtest shall continue until either the unit is no longer operable, or until conditions are obviously stable (as
: }0 R. R9 Q& s* D/ s' |, Mdetermined by no visual.
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7 _! t' [. N% v再核对一下标准看有没有答案？ [( T- z( X% J) L0 x& h0 Q
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发表于 2016-10-11 11:21
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发表于 2016-10-11 12:39
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