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8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted to cool to6 _/ E. J( I6 i* C5 | Z) ~- {6 h
room temperature and the dielectric voltage withstand test of 8.6 shall be repeated.8 J1 B. W1 Z+ I+ D, s
8.7.1.3 A risk of fire or electric shock is considered to exist with any of the following results:6 f7 d$ O. P. Z2 p0 a
a) Opening of the ground fuse, / A; v3 B" t. e1 [5 zb) Charring of the cheesecloth or tissue paper,, H9 c" c5 |8 r+ V4 l
c) Emission of flame or molten material from the unit, 4 e) [5 Y+ ]6 }6 [3 s& y% U: od) Ignition or dripping of a compound from the unit, 8 N5 W# H7 \% L2 M. k" R9 t! F; o1 I, ae) Exposure of live parts that pose a risk of electric shock under the requirements for1 P4 h9 J3 v* F8 u
accessibility of 7.2, or* g" A3 _1 E/ ]2 }6 f! ^5 s
f) Breakdown during the subsequent dielectric voltage withstand test.- u* Z$ s8 [ E
Opening of the 20A time delay fuse is acceptable provided none of the other conditions noted in (a)5 r) Y3 T/ j$ C; G6 L' Q. L0 D
through (f) occurs. / N4 O! N* `% r3 F/ B' u, s % ]# B2 w8 P7 J0 e & X: y, j2 p; d; ^' z4 U1 s- T% e0 t V/ s3 @1 J$ B* z7 |
8.7.2 Component failure test - n6 ]& N! `0 @& ?5 z+ r+ m8.7.2.1 A unit having components such as resistors, semiconductor devices, capacitors, and the like shall 2 i1 d4 X4 T( _$ pnot exhibit a risk of fire or electric shock when a simulated short circuit or open circuit is imposed. In% Q1 @# B" P _, s [. y) h" g
preparation for component failure tests, the equipment, circuit diagrams, and component specifications " {" T5 G7 U3 Uare examined to determine those fault conditions that might reasonably be expected to occur. Examples% S& c% W- [8 i: o& d2 I$ C% Z
include: short-circuits and open circuits of semiconductor devices and capacitors, faults causing open# X( K3 t4 `* C2 T$ X8 y& e
circuits of resistors and internal faults in integrated circuits., G3 y' n) x2 C1 [
Exception No. 1: Circuits in which maximum power levels have been determined to not exceed 50 W need9 a# V" U. K' K" v
not be evaluated for component failure.$ G+ K* P% e1 O$ e+ Q R, i
Exception No. 2: Devices supplied by a source operating within the limits for risk of fire and electric shock 2 ?2 F2 U: u# Y8 u( Rneed not be subject to this test. \; ^: w4 K* \% x" U4 g4 q4 b1 I6 D
8.7.2.2 Each component is to be short circuited or open circuited, one at a time (one fault per test). Each( Q; q A9 Y- v0 K' X) a
test shall continue until either the unit is no longer operable, or until conditions are obviously stable (as : Z- `) j& n' A8 z) W, X! d& Xdetermined by no visual." u" ^# a1 n U3 Q& _% Q% d
- ]9 R7 U+ H9 Z! f; u2 E( s
6 w% \4 d/ o/ u+ w8 i, ]+ i$ D* d再核对一下标准看有没有答案?, J* L9 z& H L4 _' b 作者: jsspace 时间: 2016-10-11 14:16 本帖最后由 jsspace 于 2016-10-11 14:30 编辑 7 X6 y4 ^7 a' q' S s0 _
fasten 发表于 2016-10-11 12:39 4 @+ p( n) f, t
8.7.1.2 After ultimate results have been obtained for each test, the sample shall be permitted t ...
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但奇葩的是UL内部有很多工程判断 8 Z. O" z$ Z, a0 }6 V. G这个问题,我刚刚发邮件跟UL重新确认了一下,现在的做法是如果漏液没有益处到外壳外面,且耐压测试通过,可以接受。 - n: Q+ O; `& p6 i& w v作者: 琥珀流云 时间: 2016-10-11 16:12
非常感谢,我问的UL 工程师是说不行~~,这个标准也很烂,工程师判断也不一样~·~麻烦·~~作者: jsspace 时间: 2016-10-11 17:02